After finding out about the SQRL Acorn boards on the EEVBlog Forums I picked a few up in a lot and knew this was my chance to play with some RiscV cores and run linux. The Artix-7 200T part on the CLE-215/215+ boards are just about the largest FPGAs from Xilinx you can use with their free version of Vivado (Webpack). This makes the $50-70 price point extremely enticing. The only problem is the lack of I/O. There are only 4 available 3.3V I/O with another 8 2.5V I/O designated for 4 LVDS pairs. I found there should be a way to modify the board to get those 8 2.5V pins to be 3.3V as-well. I documented this in this post.

I won’t go into detail here about how we found the schematics for the Acorn and dug into the board to find out what parts were populated. This is all on EEVBlog as previously mentioned. Moving on to the idea of running Linux on RiscV on this Acorn, shortly after I had gotten it and started playing with generating RiscV cores using ChipYard and VexRiscV I had come across Enjoy Digital’s tweet showing they had VexRiscV up with PCIe and DDR3 using LiteX. This is when I decided to use LiteX for my implementation.

So I had verified my Acorns worked in the standard PCIe to M.2 breakouts. But I didn’t want Linux to be the endpoint, I want it to have the root port! Being able to have Linux on RiscV with a PCIe root port for under what was $3000 for the original SiFive/Microsemi breakout, now $500 for the Microsemi Icicle is a very exciting proposition for me. I did order one of the Icicle kits because I think that will be a great development platform too but I started this project before I heard about that dev board. Anyway to get a root port available off the Acorn I would have to go the OTHER WAY with the PCIe breakout. These are not really available on the market. Not to mention you need to have a refclock for the PCIe root and endpoint as-well. So I got to designing my own breakout.


This board was a stepping stone for me in board design, it was my first 4 layer board, it’s the first board where I had to take into account differential trace impedence to impedence match data and clock pairs. I also had to make sure I correctly made and followed the specification and pinouts for two very high pin count connectors, the PCIe 164 pin x16 connector and an M.2 M-key connector. I also had to do termination for the HCSL clock generation and redriver/splitter chips. The other thing to include in this board was a standard 4 pin Molex power input so that the endpoint PCIe slot has 12V and to step that down to 3.3V using my favorite TPS563231, which I have used in previous designs for step down and specifically I ordered more at the time knowing I’d have designs like this in the pipeline. They can do 3A at 3.3V so it was a no-brainer to drop two on there, one for the M.2 and one for the PCIe slot.


I also added LEDs for each 3.3V rail, one for the LED_1 pin off the M.2 and one for the /ALERT pin, if its jumpered to be enabled. The Acorn doesn’t have all PCIe signals hooked to the FPGA, in particular /PEWAKE is unconnected, but /ALERT is. So /PEWAKE and /ALERT are on the opposite sides of the 3 pin jumper going to /WAKE on the PCIe slot. Allowing you to support the /WAKE pin on the PCIe slot by diverting the /ALERT pin which has no equivilant on the PCIe slot. I left the jumper to /PEWAKE just in-case a future board was designed around an M.2 formfactor and has that pin routed. The /ALERT LED can be jumpered in if you just want another blinkenlight for status.


The board powered up fine and the PCIe ref clock appears to work on the Acorn side of things! Was able to blink an LED using it! So now I had a good carrier I wanted to get Linux going on a LiteX SOC before working on a PCIe Root Port so I understood the process and the library. It took me just under 2 days to go from pulling down the LiteX libraries off github to having Linux booting. It was really quite a simple process if you follow the instructions! There was a lack of support for the Acorn in the linux-on-litex-vexriscv repository so I added it myself and am working on getting that upstreamed for others to use. I did generate my core with jtag-uart since I don’t have this in a PC to use UART over PCIe, which I believe is the default example in the target file if I understand “crossover” correctly? The only problem was I didn’t have a good FT232/2232 breakout at the time to use. So I used a clone J-Link I have and it clearly has some problems doing such data-pushing, especially when you try to do a boot over serial operation… So I had to add a microsd card, which there just so happens to be an I/O connector with 3.3V/GND and 4 3.3V I/O right next to the JTAG connection. Just enough for an spisdcard interface. I had already made up breakouts from the Pico-EZMate connectors to .1” headers by buying some of these, cutting them in half, and soldering them out to either straight through for the I/O header or to the appropriate Xilinx JTAG pinout for ease of connection to a Platform Cable. The pinouts of these connectors can be gotten from the nitefury schematics again, more on how we found that out on the EEVBlog Forum Post.

All I had to do was solder up a microsd card socket to a .1” header and plug it in. Below is how I wired it up and how the upstream support for microsd card will be supported. If you make up this adapter adding microsd card support to your SoC build should be as simple as adding –with-spi-sdcard.



So now I had the hardware setup and I had re-built the SoC gateware/software after adding support for it in the litex-boards repository locally I just had to try it. After fumbling with having a problem trying to build my own linux kernel images and having problems I decided to grab the pre-built linux images for the linux-on-litex-vexriscv. After adding these to the microsd card I had it booting but the timer wasn’t starting, I realized the emulator.bin gets built with your gateware/software for the SoC. So I threw that on the microsd card in place of the pre-built and I was able to get linux to boot!

Now I just have to see about adding root port mode support to litepcie, but it may be awhile since I am still relatively new to migen and I still have a lot of the litex source to read to understand its capabilities fully. I’ve also spent a few days reading over the PCIe base spec and Linux source drivers for PCIe to understand how that all works.

More on that in another post later…

-Connor Krukosky